During the manufacture of a display panel, some Testing Element Groups (TEGs) may be arranged at a non-display area of the display panel, so as to monitor the characteristic values at an active area (AA) of the display panel. These TEGs are configured to test performances of thin film transistors (TFTs) of the display panel as well as resistances of gate metal lines and source-drain (SD) metal lines (each line resistance can indicate thickness uniformity of a metal layer).
As shown in FIG. 1, which is a schematic view showing the TEG on an array substrate in the related art, the TEG includes a TFT 101, a TFT 102, a gate metal line 103, an SD metal line 104, and 12 pads (i.e. testing contact electrodes corresponding to S, D and G in FIG. 1). Each TFT corresponds to three testing contact electrodes and each metal line corresponds to two testing contact electrodes, with two testing contact electrodes being unused.
In FIG. 1, each element to be tested (i.e., the TFT, the gate metal line or the SD metal line) corresponds to at least two independent testing contact electrodes. As a result, the testing cost is relatively high, and a large space may be occupied.